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Article
2000
André Windisch and Schneider and Mades and Dieter Monjau and Manfred Glesner and Hammer and Wolfgang Ecker
Eine flexible Simulationsumgebung für System-On-Chip Design
IN Informationstechnik und Technische Informatik (it+ti), page 43 - 53, Oldenbourg Verlag, München, Deutschland, 2000.
Eine flexible Simulationsumgebung für System-On-Chip Design
IN Informationstechnik und Technische Informatik (it+ti), page 43 - 53, Oldenbourg Verlag, München, Deutschland, 2000.
InProceedings
2000
Schneider and Mades and Manfred Glesner and André Windisch and Wolfgang Ecker
An Open VHDL-AMS Simulation Framework
IN IEEE/ACM International Workshop on Behavioral Modeling and Simulation (BMAS 2000), page 89 - 94, IEEE Computer Society, October 2000. ISBN: 0-7695-0893-6
An Open VHDL-AMS Simulation Framework
IN IEEE/ACM International Workshop on Behavioral Modeling and Simulation (BMAS 2000), page 89 - 94, IEEE Computer Society, October 2000. ISBN: 0-7695-0893-6
Karayiannis and Mades and André Windisch and Schneider and Wolfgang Ecker
Using XML for Represantation and Visualization of Elaborated VHDL-AMS Models
IN Proceedings of the VHDL International Users Forum (VIUF), page 83 - 87, IEEE Computer Society, October 2000. ISBN: 0-7695-0890-1
Using XML for Represantation and Visualization of Elaborated VHDL-AMS Models
IN Proceedings of the VHDL International Users Forum (VIUF), page 83 - 87, IEEE Computer Society, October 2000. ISBN: 0-7695-0890-1
Wolfgang Ecker and André Windisch and Mades and Schneider and Yang
Gated Clocks in RT-Synthesis and Simulation
IN Proceedings of the VHDL International Users Forum (VIUF), page 59 - 63, IEEE Computer Society, October 2000. ISBN: 0-7695-0890-1
Gated Clocks in RT-Synthesis and Simulation
IN Proceedings of the VHDL International Users Forum (VIUF), page 59 - 63, IEEE Computer Society, October 2000. ISBN: 0-7695-0890-1
Schneider and Mades and André Windisch and Manfred Glesner and Wolfgang Ecker
Anatomy of a VHDL-AMS Environment.
IN Proceedings of the Forum on Design Languages (FDL), page 159 - 165, September 2000. ISBN: 3-0000-6540-7
Anatomy of a VHDL-AMS Environment.
IN Proceedings of the Forum on Design Languages (FDL), page 159 - 165, September 2000. ISBN: 3-0000-6540-7
André Windisch and Schneider and Mades and Dieter Monjau and Wolfgang Ecker
A VHDL-Centric Mixed-Language Simulation Environment
IN Proceedings of the Forum on Design Languages (FDL), page 339 - 345, September 2000. ISBN: 3-0000-6540-7
A VHDL-Centric Mixed-Language Simulation Environment
IN Proceedings of the Forum on Design Languages (FDL), page 339 - 345, September 2000. ISBN: 3-0000-6540-7
Karayiannis and Mades and André Windisch and Schneider and Wolfgang Ecker
Using XML in VHDL Analysis and Simulation
IN Proceedings of the Forum on Design Languages (FDL), page 117 - 122, September 2000. ISBN: 3-0000-6540-7
Using XML in VHDL Analysis and Simulation
IN Proceedings of the Forum on Design Languages (FDL), page 117 - 122, September 2000. ISBN: 3-0000-6540-7
Schneider and André Windisch and Mades and Manfred Glesner and Dieter Monjau and Wolfgang Ecker
A System-Level Simulation Environment for System-On-Chip Design
IN Proceedings of 13th Annual IEEE International ASIC/SOC Conference, page 58 - 62, September 2000. ISBN: 0-7803-6598-4
A System-Level Simulation Environment for System-On-Chip Design
IN Proceedings of 13th Annual IEEE International ASIC/SOC Conference, page 58 - 62, September 2000. ISBN: 0-7803-6598-4
Yang and André Windisch and Schneider and Mades and Wolfgang Ecker
IVE: An Internet based Distributed VHDL Environment
IN Proceedings of 13th Annual IEEE International ASIC/SOC Conference, page 131 - 135, September 2000. ISBN: 0-7803-6598-4
IVE: An Internet based Distributed VHDL Environment
IN Proceedings of 13th Annual IEEE International ASIC/SOC Conference, page 131 - 135, September 2000. ISBN: 0-7803-6598-4
Schneider and Mades and André Windisch and Manfred Glesner and Wolfgang Ecker
A JAVA-based Mixed-Signal Design Environment
IN Proceedings of the XIII Symposium on Integrated Circuits and System Design (Chip In The Jungle), page 301 - 306, IEEE Computer Society, September 2000. ISBN: 0-7695-0843-X
A JAVA-based Mixed-Signal Design Environment
IN Proceedings of the XIII Symposium on Integrated Circuits and System Design (Chip In The Jungle), page 301 - 306, IEEE Computer Society, September 2000. ISBN: 0-7695-0843-X
Yang and André Windisch and Schneider and Mades and Wolfgang Ecker
IVE: An Environment for Internet Based distributed VHDL Design
IN Proceedings of the 16th World Computer Congress, page 516 - 525, IEEE Computer Society, August 2000. ISBN: 3-9018-8208-1
IVE: An Environment for Internet Based distributed VHDL Design
IN Proceedings of the 16th World Computer Congress, page 516 - 525, IEEE Computer Society, August 2000. ISBN: 3-9018-8208-1
Wolfgang Ecker and Mike Heuchling and Mades and Schneider and André Windisch and Yang
Using XML for VHDL Model Representation
IN Proceedings of the 16th World Computer Congress, page 526 - 535, IEEE Computer Society, August 2000. ISBN: 3-9018-8208-1
Using XML for VHDL Model Representation
IN Proceedings of the 16th World Computer Congress, page 526 - 535, IEEE Computer Society, August 2000. ISBN: 3-9018-8208-1
Mades and Schneider and André Windisch and Wolfgang Ecker
Elaboration of Hierarchical VHDL-AMS Models for Mixed-Signal Simulation
IN Proceedings of the International HDL Conference and Exhibition (HDLCON), page 111 - 117, The Printig House, US, March 2000.
Elaboration of Hierarchical VHDL-AMS Models for Mixed-Signal Simulation
IN Proceedings of the International HDL Conference and Exhibition (HDLCON), page 111 - 117, The Printig House, US, March 2000.
Wolfgang Ecker and Mike Heuchling and Mades and Schneider and André Windisch and Yang
VXML: VHDL-Design Hardware Representation in XML
IN ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, page 129 - 140, VDE Verlag, Berlin, Offenbach, February 2000. ISBN: 3-8007-2524-X
VXML: VHDL-Design Hardware Representation in XML
IN ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, page 129 - 140, VDE Verlag, Berlin, Offenbach, February 2000. ISBN: 3-8007-2524-X
1999
Wolfgang Ecker and Mike Heuchling and Mades and Schneider and Schneider and André Windisch and Yang and Zambaldi
VHDL2HYPER - A highly flexible Hypertext Generator for VHDL Models
IN Proceedings of the VHDL International Users Forum (VIUF), page 57 - 62, IEEE Computer Society, October 1999. ISBN: 0-7695-0334-9
VHDL2HYPER - A highly flexible Hypertext Generator for VHDL Models
IN Proceedings of the VHDL International Users Forum (VIUF), page 57 - 62, IEEE Computer Society, October 1999. ISBN: 0-7695-0334-9
Wolfgang Ecker and Manfred Glesner and Hollstein and Mades and Schneider and Theisen and André Windisch and Yang
A Flexible Connected Data System for VHDL Source Code Analysis, Transformation and Processing
IN GMM Fachbericht Entwurf integrierter Schaltungen, 9. E.I.S. Workshop, VDE Verlag, Berlin, Offenbach, September 1999.
A Flexible Connected Data System for VHDL Source Code Analysis, Transformation and Processing
IN GMM Fachbericht Entwurf integrierter Schaltungen, 9. E.I.S. Workshop, VDE Verlag, Berlin, Offenbach, September 1999.
Mades and Schneider and André Windisch and Yang and Wolfgang Ecker
A Scalable Multithreaded Compiler Frontend
IN Parallel Computing - Fundamentals and Applications - Proceedings of the International Conference (ParCo99), page 722 - 729, August 1999. ISBN: 1-86094-235-0
A Scalable Multithreaded Compiler Frontend
IN Parallel Computing - Fundamentals and Applications - Proceedings of the International Conference (ParCo99), page 722 - 729, August 1999. ISBN: 1-86094-235-0
André Windisch and Wolfgang Ecker and Hammer and Mades and Schneider and Yang
An Adaptable VHDL-AMS Compiler Front End
IN Proceedings Second International Forum on Design Languages FDL 99, page 71 - 80, August 1999. ISBN: 2-84010-033-9
An Adaptable VHDL-AMS Compiler Front End
IN Proceedings Second International Forum on Design Languages FDL 99, page 71 - 80, August 1999. ISBN: 2-84010-033-9
Wolfgang Ecker and Mades and Schneider and André Windisch and Yang
A Makefile Generator for VHDL Models under Consideration of Hierarchical Names, Identifier-Visibility and Identifier-Hiding
IN Proceedings Second International Forum on Design Languages FDL 99, page 81 - 90, August 1999. ISBN: 2-84010-033-9
A Makefile Generator for VHDL Models under Consideration of Hierarchical Names, Identifier-Visibility and Identifier-Hiding
IN Proceedings Second International Forum on Design Languages FDL 99, page 81 - 90, August 1999. ISBN: 2-84010-033-9
Wolfgang Ecker and Mades and Schneider and André Windisch and Yang
A Dependency Graph for VHDL Design Files and Design Units and its Application in a VHDL Design Environment
IN Proceedings of the International HDL Conference and Exhebition (HDLCON), page 111 - 117, April 1999.
A Dependency Graph for VHDL Design Files and Design Units and its Application in a VHDL Design Environment
IN Proceedings of the International HDL Conference and Exhebition (HDLCON), page 111 - 117, April 1999.
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