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2000
Gated Clocks in RT-Synthesis and Simulation
IN Proceedings of the VHDL International Users Forum (VIUF), page 59 - 63, IEEE Computer Society, October 2000. ISBN: 0-7695-0890-1
IVE: An Internet based Distributed VHDL Environment
IN Proceedings of 13th Annual IEEE International ASIC/SOC Conference, page 131 - 135, September 2000. ISBN: 0-7803-6598-4
IVE: An Environment for Internet Based distributed VHDL Design
IN Proceedings of the 16th World Computer Congress, page 516 - 525, IEEE Computer Society, August 2000. ISBN: 3-9018-8208-1
Using XML for VHDL Model Representation
IN Proceedings of the 16th World Computer Congress, page 526 - 535, IEEE Computer Society, August 2000. ISBN: 3-9018-8208-1
VXML: VHDL-Design Hardware Representation in XML
IN ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, page 129 - 140, VDE Verlag, Berlin, Offenbach, February 2000. ISBN: 3-8007-2524-X
1999
VHDL2HYPER - A highly flexible Hypertext Generator for VHDL Models
IN Proceedings of the VHDL International Users Forum (VIUF), page 57 - 62, IEEE Computer Society, October 1999. ISBN: 0-7695-0334-9
A Flexible Connected Data System for VHDL Source Code Analysis, Transformation and Processing
IN GMM Fachbericht Entwurf integrierter Schaltungen, 9. E.I.S. Workshop, VDE Verlag, Berlin, Offenbach, September 1999.
A Scalable Multithreaded Compiler Frontend
IN Parallel Computing - Fundamentals and Applications - Proceedings of the International Conference (ParCo99), page 722 - 729, August 1999. ISBN: 1-86094-235-0
An Adaptable VHDL-AMS Compiler Front End
IN Proceedings Second International Forum on Design Languages FDL 99, page 71 - 80, August 1999. ISBN: 2-84010-033-9
A Makefile Generator for VHDL Models under Consideration of Hierarchical Names, Identifier-Visibility and Identifier-Hiding
IN Proceedings Second International Forum on Design Languages FDL 99, page 81 - 90, August 1999. ISBN: 2-84010-033-9
A Dependency Graph for VHDL Design Files and Design Units and its Application in a VHDL Design Environment
IN Proceedings of the International HDL Conference and Exhebition (HDLCON), page 111 - 117, April 1999.
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